//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
//
//
// (C) Copyright 2006 Marvell International Ltd.
// All Rights Reserved
//

#include <windows.h>
#include <oal.h>

#include "monahans_base_regs.h"
#include "xllp_defs.h"
#include "xllp_clkmgr.h"
#include "xllp_mfp_proc.h"
#include "Isram.h"

static void (* pfnEnableSRAMPowerDomain) (void);   // function pointer to refresh watchdog
static void (* pfnDisableSRAMPowerDomain) (void);   // function pointer to refresh watchdog


void RegisterPowerDomainFunctions(
	void (* pfnEnablePD)(void), 
	void (* pfnDisablePD)(void)
	)
{
	RETAILMSG(TRUE, (L"RegisterPowerDomainFunctions() called.\r\n"));

	pfnEnableSRAMPowerDomain = pfnEnablePD;
	pfnDisableSRAMPowerDomain = pfnDisablePD;
}

BOOL EnableSRAM()
{
	// Clock Vars
	volatile XLLP_CLKMGR_T *pCLKReg;
    BOOL retVal = FALSE;

    if (pfnEnableSRAMPowerDomain)
        pfnEnableSRAMPowerDomain(); //EnableSRAMPowerDomain();

	// Enable Clock
	//
//	RETAILMSG(TRUE, (L"Enable Internal SRAM Clock.\r\n"));
	pCLKReg = (XLLP_CLKMGR_T *)OALPAtoVA(MONAHANS_BASE_REG_PA_CLKMGR, FALSE);
	retVal = XllpClockEnable((P_XLLP_CLKMGR_T)pCLKReg, XLLP_CLK_ISC, XLLP_TRUE);   

    return retVal;
}


void DisableSRAM()
{
	// Clock vars
	//
	volatile XLLP_CLKMGR_T *pCLKReg;

	// Disable Clock
	//
	//RETAILMSG(TRUE, (L"Disable Internal SRAM Clock\r\n"));
	pCLKReg = (XLLP_CLKMGR_T *)OALPAtoVA(MONAHANS_BASE_REG_PA_CLKMGR, FALSE);
                                                      
	XllpClockEnable((P_XLLP_CLKMGR_T)pCLKReg, XLLP_CLK_ISC, XLLP_FALSE);

    if (pfnDisableSRAMPowerDomain)
        pfnDisableSRAMPowerDomain(); // DisableSRAMPowerDomain();
}


void SaveSRAMDataToDDR(XLLP_UINT8_T *pucDDRAddr, XLLP_UINT32_T ulDataBytes)
{
	volatile XLLP_UINT8_T *pucSRAMAddr = NULL;

    /* This ISRAM should match with the IMM driver */
    pucSRAMAddr = (XLLP_UINT8_T *)OALPAtoVA(ISRAM_IMM_START_ADDR, FALSE);
    memcpy((LPVOID)pucDDRAddr, (LPVOID)pucSRAMAddr, ulDataBytes);

}

void RestoreSRAMDataFromDDR(XLLP_UINT8_T *pucDDRAddr, XLLP_UINT32_T ulDataBytes)
{
 	volatile XLLP_UINT8_T *pucSRAMAddr = NULL;

    /* This ISRAM should match with the IMM driver */
    pucSRAMAddr = (XLLP_UINT8_T *)OALPAtoVA(ISRAM_IMM_START_ADDR, FALSE);
    memcpy((LPVOID)pucSRAMAddr, (LPVOID)pucDDRAddr, ulDataBytes);
}
